代码搜索:RS编码

找到约 10,000 项符合「RS编码」的源代码

代码结果 10,000
www.eeworm.com/read/327360/3462568

h platform_aix_rs_ibmcxx.h

//%2006//////////////////////////////////////////////////////////////////////// // // Copyright (c) 2000, 2001, 2002 BMC Software; Hewlett-Packard Development // Company, L.P.; IBM Corp.; The Open Gro
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h platform_aix_rs_ibmcxx.h

//%2004//////////////////////////////////////////////////////////////////////// // // Copyright (c) 2000, 2001, 2002 BMC Software; Hewlett-Packard Development // Company, L.P.; IBM Corp.; The Open Gro
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h platform_aix_rs_ibmcxx.h

//%2003//////////////////////////////////////////////////////////////////////// // // Copyright (c) 2000, 2001, 2002 BMC Software, Hewlett-Packard Development // Company, L. P., IBM Corp., The Open G
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lso fpga_40rs232.lso

work
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bgn fpga_40rs232.bgn

Release 6.2i - Bitgen G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "fpga_40RS232.ncd". "fpga_40RS232" is an NCD, version
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ut fpga_40rs232.ut

-w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:Pu
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drc fpga_40rs232.drc

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net CLK1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip
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prj fpga_40rs232.prj

verilog work serial.v verilog work diag.v verilog work fpga_40XRS232.v
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par fpga_40rs232.par

Release 6.2i Par G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. TOMWANG:: Sun Feb 26 16:53:28 2006 C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_40RS232_map.ncd fpg
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pcf fpga_40rs232.pcf

SCHEMATIC START ; // created by map version G.28 on Sun Feb 26 16:53:27 2006 COMP "reset1" LOCATE = SITE "P163" LEVEL 1; COMP "CTS" LOCATE = SITE "P127" LEVEL 1; COMP "RD" LOCATE = SITE "P13