代码搜索：RAM

找到约 10,000 项符合「RAM」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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xcp ram.xcp

# Xilinx CORE Generator 6.3.03i SELECT Dual_Port_Block_Memory Spartan3 Xilinx,_Inc. 6.1 CSET primitive_selection = Optimize_For_Area CSET port_a_active_clock_edge = Rising_Edge_Triggered CSET port
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vho ram.vho

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used -- -- solely for design, simulation
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edn ram.edn

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2007 7 26 10 24 50) (author "Xilinx, Inc.") (program "Xilinx CORE Generator" (version "X
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xco ram.xco

# Xilinx CORE Generator 6.3.03i # Username = winwalk # COREGenPath = D:\Program Files\Xilinx\coregen # ProjectPath = E:\Documentation\Digital\PROJECT\QAM\MAC\TEST_TRAN\ver1.7-mux # ExpandedProject
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v ram.v

/******************************************************************************* * This file is owned and controlled by Xilinx and must be used * * solely for design, simulation,
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qsf ram.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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pof ram.pof

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sof ram.sof

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vhd ram.vhd

---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram
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qws ram.qws

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1 [ProjectWorkspace.Frames.
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