ram.vhd

来自「RAM存储器的源程序」· VHDL 代码 · 共 41 行

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram is
    Port ( addr : in  STD_LOGIC_VECTOR (4 downto 0);--地址选择
           wr : in  STD_LOGIC;				--写
           rd : in  STD_LOGIC;				--读
           cs : in  STD_LOGIC;				--片选
           datain : in  STD_LOGIC_VECTOR (7 downto 0);
           dataout : out  STD_LOGIC_VECTOR (7 downto 0));
end ram;

architecture Behavioral of ram is
	type t_mem is array(0 to 31) of STD_LOGIC_VECTOR (7 downto 0);--存储空间
	signal data1 : t_mem;
	signal addr1:integer range 0 to 31;
begin
	addr1<=CONV_INTEGER(addr);
	
	process (wr,cs,addr1,data1,datain)--写
	begin  
		if (cs='0' and wr='1') then
			data1(addr1)<=datain;
		end if;
	end process;
	
	process (rd,cs,addr1,data1)--读
begin  
   if (cs='0' and rd='1') then
      dataout<=data1(addr1);
   else
      dataout<=(others=>'Z');
   end if;
end process;

end Behavioral;