代码搜索:RAM配置

找到约 10,000 项符合「RAM配置」的源代码

代码结果 10,000
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c ds12887.c

#include #include #define uchar unsigned char #define uint unsigned int //============================ #define C8155 XBYTE[0x7000] #define PA XBYTE[0x7001] #define PB XBYTE
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v or1200_spram_2048x32_bw.v

////////////////////////////////////////////////////////////////////// //// //// //// Generic Single-Port Synchronous RAM with byte write
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txt mc8051_ram_flist.txt

# Output products list for mc8051_ram_flist.txt mc8051_ram.edn mc8051_ram.vhd mc8051_ram.vho mc8051_ram.v mc8051_ram.veo mc8051_ram.asy mc8051_ram.sym mc8051_ram.xco
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cmd emuinit.cmd

;--------------------------------------- ; TMS320F240 Emulator Init Command File ;--------------------------------------- mr ;------------- ; DATA MEMORY ;------------- ma 0x0000,1,0x005F,ram
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txt mc8051_ram_flist.txt

# Output products list for mc8051_ram.edn mc8051_ram.vhd mc8051_ram.vho mc8051_ram.v mc8051_ram.veo mc8051_ram.asy mc8051_ram.sym mc8051_ram.xco mc8051_ram_flist.txt
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vhd init_8_ram16x1s.vhd

-- -- Module: INIT_8_RAM16x1s -- Design: CAM_Top -- VHDL code: VIRTEX primitives instantiation -- -- Synthesis Synopsys FPGA Express ver. 3.2 -- Use of "pragma synthesis_off/on" and attribut
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v init_8_ram16x1s.v

// // Module: INIT_8_RAM16x1s // Design: CAM_Top // Verilog code: RTL / Combinatorial // // Synthesis_tool Synopsys FPGA Express ver. 3.3 // Enable Synthesis Option: Verilog Pre-pro
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asm systemtimer.asm

;;***************************************************************************** ;;***************************************************************************** ;; Filename: SystemTimer.asm ;; V
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asm usb.asm

CPU 63413 label: XPAGEON ;======================================================================== ; FILE: usb.asm ; ; This file includes all the files necessary to build
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inc malloc.inc

;------------------------------------------------------------------------ ; MALLOC.INC ;------------------------------------------------------------------------ ; Global memory allocation listing/u