代码搜索：RAM配置
找到约 10,000 项符合「RAM配置」的源代码
代码结果 10,000
www.eeworm.com/read/235392/14072815
v or1200_xcv_ram32x8d.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Xilinx Virtex RAM 32x8D
www.eeworm.com/read/204857/15332559
lnp blinky.lnp
".\ram\str71x.o" ".\ram\71x_it.o" ".\ram\retarget.o" "..\..\..\..\LIB\ST\STR71xR.LIB" ".\ram\blinky.o" --strict --scatter ".\RAM\Blinky.sct"
--map --xref --callgraph --symbols
--info sizes --info
www.eeworm.com/read/433021/8551915
vhd 带ram和控制处理器的数字延时单元.vhd
--Top-level Digital Delay Unit including RAM and control process
--VHDL model of a ram-based analogue delay system.
USE WORK.rampac.ALL;
USE WORK.adcpac.ALL;
ENTITY digdel2 IS
PORT(clear : IN BIT; --c
www.eeworm.com/read/364925/9887983
cmd tms320uc5402.cmd
/*************************************************************
*Copyright (c) 2005,北京精仪达盛科技有限公司研发部
*All rights reserved
*
*文件名称：tms320uc5402.cmd
*文件标示：
*摘 要：本文件内容为tms320uc5402 dsp CPU板的
www.eeworm.com/read/274972/10842355
c nvram.c
/* nvRam.c - non-volatile RAM library */
/* Copyright 1984-1996 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01f,18jun96,wlf doc: cleanup.
01e
www.eeworm.com/read/326753/13118980
cmd tms320uc5402.cmd
/*************************************************************
*Copyright (c) 2005,北京精仪达盛科技有限公司研发部
*All rights reserved
*
*文件名称：tms320uc5402.cmd
*文件标示：
*说 明：本文件内容为tms320uc5402 dsp CPU板的
www.eeworm.com/read/326751/13119045
cmd tms320uc5402.cmd
/*************************************************************
*Copyright (c) 2005,北京精仪达盛科技有限公司研发部
*All rights reserved
*
*文件名称：tms320uc5402.cmd
*文件标示：
*摘 要：本文件内容为tms320uc5402 dsp CPU板的
www.eeworm.com/read/169681/5416001
c nvram.c
/* nvRam.c - non-volatile RAM library */
/* Copyright 1984-1996 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01f,18jun96,wlf doc: cleanup.
01e
www.eeworm.com/read/266600/11217142
asm dmx512rx.asm
;;*****************************************************************************
;;*****************************************************************************
;; FILENAME: `@INSTANCE_NAME`.asm
;;
www.eeworm.com/read/318037/13489219
vhd tb.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
entity c is
end;
architecture behav of c is
component urisc
PORT(READ_FROM_RAM:in std_logic_vector(7 downto 0);
WRITE_TO_RAM:out std_l