带ram和控制处理器的数字延时单元.vhd

含有各类寄存器

--Top-level Digital Delay Unit including RAM and control process
--VHDL model of a ram-based analogue delay system.
USE WORK.rampac.ALL;
USE WORK.adcpac.ALL;
ENTITY digdel2 IS
PORT(clear : IN BIT; --clears address counter
offset : IN addr10; --delay control
sigin : IN analogue; --signal input
sigout : INOUT analogue); --signal output
END digdel2;
ARCHITECTURE block_struct OF digdel2 IS
COMPONENT adc16
PORT(vin : IN analogue; digout : OUT data16;
sc : IN BIT; busy : OUT BIT);
END COMPONENT;
COMPONENT dac16
PORT(vout : INOUT analogue; digin : IN data16;
en : IN BIT);
END COMPONENT;
SIGNAL address : addr10; --pointer to ram location
SIGNAL ram_data_out : data16; --data output of ram
SIGNAL ram_data_in : data16; --data input to ram
SIGNAL clock,cs,write,suboff,adcsc,dacen,adcbusy : BIT; --internal controls
BEGIN
--start conversion on positive edge of 'clock'at beginning of cycle
adcsc <= NOT clock; --|__________----------|
adc1 : adc16 PORT MAP (sigin,ram_data_in,adcsc,adcbusy);
cs <= '1'; --enable ram device
ram:BLOCK -- 16-bit * 1024 location RAM
BEGIN
ram_proc:PROCESS(cs,write,address,ram_data_in)
VARIABLE ram_data : ram_array;
VARIABLE ram_init : BOOLEAN := FALSE;
BEGIN
IF NOT(ram_init) THEN --initialise ram locations
FOR i IN ram_data'RANGE LOOP
ram_data(i) := 0;
END LOOP;
ram_init := TRUE;
END IF;
IF cs = '1' THEN
IF write = '1' THEN
ram_data(address) := ram_data_in;
END IF;
ram_data_out <= ram_data(address);
ELSE
ram_data_out <= z_val;
END IF;
END PROCESS;
END BLOCK ram;
dac1 : dac16 PORT MAP (sigout,ram_data_out,dacen);
-- concurrent statement for 'suboff' (subtract offset) signal for counter
suboff <= clock; --|----------__________|
cntr10:BLOCK --10-bit address counter with offset control
SIGNAL count : addr10 := 0;
BEGIN --dataflow model of address counter
count <= 0 WHEN clear = '1' ELSE
((count + 1) MOD 1024) WHEN (clock'EVENT AND clock = '1')
ELSE count;
address <= count WHEN suboff = '0'
ELSE (count - offset) WHEN ((count - offset) >= 0)
ELSE (1024 - ABS(count - offset));
END BLOCK cntr10;
control_waves:PROCESS --process to generate system control waveforms
BEGIN
clock <= TRANSPORT '1';
clock <= TRANSPORT '0' AFTER 10 us; --|----------__________|
dacen <= TRANSPORT '1',
'0' AFTER 5 us; --|-----_______________|
write <= TRANSPORT '1' AFTER 13 us, --|_____________----___|
'0' AFTER 17 us;
WAIT FOR 20 us;
END PROCESS control_waves;
END block_struct;