tb.vhd

来自「用代码来控制urisc控制器」· VHDL 代码 · 共 58 行

Library IEEE;
use IEEE.std_logic_1164.all;

entity c is
end;

architecture behav of c is
 component urisc
   PORT(READ_FROM_RAM:in std_logic_vector(7 downto 0);
        WRITE_TO_RAM:out std_logic_vector(7 downto 0);
        ADDRESS:out std_logic_vector(7 downto 0);
        WRITE:out std_logic;
        READ:out std_logic;
        run,clk: in std_logic);
 end component;

component ram is
 port( RAM_IN:in std_logic_vector(7 downto 0);
         RAM_OUT:out std_logic_vector(7 downto 0);
         WRITER,READR:in std_logic;
         ADDRESS_RAM:in std_logic_vector(7 downto 0)
         );
   end component;


  signal READ,WRITE,run: std_logic;
  signal READ_FROM_RAM,WRITE_TO_RAM: std_logic_vector(7 downto 0);
  signal ADDRESS:std_logic_vector(7 downto 0);
  signal RAM_IN,RAM_OUT:std_logic_vector(7 downto 0);
  signal ADDRESS_RAM:std_logic_vector(7 downto 0);
   signal WRITER,READR: std_logic;
   signal clk:std_logic:='0';

begin
  uut_a: urisc port map (READ_FROM_RAM,WRITE_TO_RAM,ADDRESS,WRITE,READ,run,clk);
  uut_b:  ram  port map  (RAM_IN,RAM_OUT,WRITER,READR,ADDRESS_RAM);
    READ_FROM_RAM<=RAM_OUT;
    RAM_IN<=WRITE_TO_RAM;
    ADDRESS_RAM<=ADDRESS;
    WRITER<=WRITE;
    READR<=READ;
  process
   begin
     clk <='0';
     wait for 100 ns;
     clk <='1';
     wait for 100 ns;
   end process;
 run<='1','0' after 195 ns;
end;


configuration cfg_tb_cc of c is
for behav
end for;
end;