代码搜索：QL
找到约 821 项符合「QL」的源代码
代码结果 821
www.eeworm.com/read/137072/13346623
hier_info clock.hier_info
|clock
clk => q1l[2]~reg0.CLK
clk => q1l[1]~reg0.CLK
clk => q1l[0]~reg0.CLK
clk => q1h[3]~reg0.CLK
clk => q1h[2]~reg0.CLK
clk => q1h[1]~reg0.CLK
clk => q1h[0]~reg0.CLK
clk => q2l[3]~reg0.CLK
www.eeworm.com/read/152843/5662978
makefile
EXTRA_CFLAGS += -DUNIQUE_FW_NAME
qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
qla_dbg.o qla_sup.o qla_rscn.o qla_attr.o
qla2100-y := ql2100.o ql2100_fw.o
qla2200-y :=
www.eeworm.com/read/152843/5662996
h qla_dbg.h
/*
* QLogic Fibre Channel HBA Driver
* Copyright (c) 2003-2005 QLogic Corporation
*
* See LICENSE.qla2xxx for copyright and licensing details.
*/
/*
* Driver debug definitions.
*/
/* #define Q
www.eeworm.com/read/182656/9197997
asm paixu.asm
ORG 09B0H
QUE: MOV R3,#50H
QUE1: MOV A,R3
MOV R0,A
MOV R7,#0AH
CLR 00H
MOV A,@R0
QL2: INC R0
MOV R2,A
CLR C
MOV 22H,@R0
CJNE A,22H,QL3
SETB C
QL3: MOV A,R2
JC QL1
SETB 00H
www.eeworm.com/read/165787/10051491
src init_7820.src
; .\init_7820.SRC generated from: init_7820.c
; COMPILER INVOKED BY:
; C:\KEIL\C51\BIN\C51.EXE init_7820.c OPTIMIZE(0,SPEED) BROWSE DEBUG OBJECTEXTEND SRC(.\init_7820.SRC)
NAME INIT_7820
www.eeworm.com/read/353809/10416719
vhd cntm24v.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm24v is
port(clk,clr,en:in std_logic;
cont:out std_logic;
qh,ql:out std_logic_vector(3 downto 0));
end
www.eeworm.com/read/353809/10417065
vhd cntm60v.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntm60v is
port(clk,clr,en:in std_logic;
cont:out std_logic;
qh,ql:out std_logic_vector(3 downto 0));
end
www.eeworm.com/read/449912/7494063
vhd hour.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HOUR IS
PORT( EN2,EN,CP,RES:IN STD_LOGIC;
HH,HL:OUT STD_LOGIC_VECTOR(3 DO
www.eeworm.com/read/449907/7494508
vhd hour.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HOUR IS
PORT( EN2,EN,CP,RES:IN STD_LOGIC;
HH,HL:OUT STD_LOGIC_VECTOR(3 DO
www.eeworm.com/read/444302/7614345
c test.c
ORG 0000H
AJMP MAIN
ORG 0030H
MAIN: MOV R3,#50H
QUE1: MOV A,R3 ;指针送R0
MOV R0,A
MOV R7,#0AH ;长度送R7
CLR 00H ;标志位为0