hour.vhd

数字钟的VHDL源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HOUR IS
PORT( EN2,EN,CP,RES:IN STD_LOGIC;
     HH,HL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END HOUR;
ARCHITECTURE STR OF HOUR IS
SIGNAL QH,QL:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CP,EN2,EN,RES)
BEGIN
	IF RES='0'THEN
		QH<="0000";
		QL<="0000";
	ELSIF(CP'EVENT AND CP='1')THEN
		IF(EN='1'OR EN2='1')THEN
			IF QH>1 THEN
				IF QL>2 THEN
					QH<="0000";
					QL<="0000";
				ELSE QL<=QL+1;
				END IF;
			ELSIF(QL=9)THEN
					QL<="0000";
					QH<=QH+1;
			ELSE QL<=QL+1;
			END IF;
		END IF;
	END IF;
END PROCESS;
HH<=QH;
HL<=QL;
END STR;