代码搜索：Process
找到约 10,000 项符合「Process」的源代码
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www.eeworm.com/read/337633/12353518
txt ctr 1101.txt
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ctr is
port(
reset : in std_logic; --input only reset the system
clk : in std_logic; --input
www.eeworm.com/read/337633/12353540
vhd ctr.vhd
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ctr is
port(
reset : in std_logic; --input only reset the system
clk : in std_logic; --input
www.eeworm.com/read/149607/12362940
vhd latchinf.vhd
-- MAX+plus II VHDL Example
-- Latch Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
www.eeworm.com/read/149607/12362988
vhd uart_ls.vhd
----------------------------------------------------------------
--
-- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.
--
-------------------------------------------------------
www.eeworm.com/read/337440/12368838
ex conffiles.ex
#
# If you want to use this conffile, remove all comments and put files that
# you want dpkg to process here using their absolute pathnames.
# See the policy manual
#
# for example:
# /etc/rtpproxy/rt
www.eeworm.com/read/149423/12380173
cs print.cs
using System;
using System.Windows.Forms;
using System.Collections ;
namespace Interpreter
{
///
/// Summary description for Print.
///
public class Print :Verb
{
www.eeworm.com/read/337134/12388579
plg time.plg
礦ision2 Build Log
Project:
C:\tools\实验板\实验例程\8583读写\time.uv2
Project File Date: 06/16/2005
Output:
Build target 'Target 1'
compiling time.c..
www.eeworm.com/read/250613/12396704
vhd fd.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fd is
port(clk:in std_logic;
key:in std_logic;
keyout:out std_logic);
end fd;
architecture rt
www.eeworm.com/read/250454/12405522
vhd mult242.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult242 is
PORT
( clk : IN STD_LOGIC;
Din : IN SIGNED (8 DOWNTO 0);
Dout : OUT SIGNED (15 DOWNTO 0));
END
www.eeworm.com/read/250454/12405579
rpt fir.map.rpt
Analysis & Synthesis report for fir
Tue Jul 10 15:25:45 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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