📄 fd.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fd is
port(clk:in std_logic;
key:in std_logic;
keyout:out std_logic);
end fd;
architecture rt of fd is
signal q:std_logic_vector(24 downto 0);
signal jsq:integer range 0 to 60;
begin
process(clk)
begin
if(clk'event and clk='1')then
if(q=20000000)then
q<="0000000000000000000000000";
else
q<=q+"0000000000000000000000001";
end if;
end if;
end process;
process(q)
begin
if(q(14)'event and q(14)='1')then
if(key='1')then
if(jsq=35)then
jsq<=jsq;
else
jsq<=jsq+1;
end if;
else
jsq<=0;
end if;
end if;
if(jsq=35)then
keyout<='1';
else
keyout<='0';
end if;
end process;
end rt;
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