ctr 1101.txt

用cpld控制时序通过usb传送数据到pc机的vhdl源码

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ctr is
  port(
	  reset		:	in  std_logic;   --input only reset the system
	  clk		:	in  std_logic;   --input only the globle clk
	  ifclk		:	in  std_logic;   --input only synchroniation clk with USB
	  empty		:	in  std_logic;   --input only empty status of the fifos
	  busy		:	in  std_logic;   --input only A/D conversion flag
	  led1		:	out std_logic;   --output only A/D conversion indicator light
	  led2		:	out std_logic;   --output only error indicator light
	  r_c		:	out std_logic;   --the signal that start a new conversion 
	  ctr		:	out std_logic;   --swich the amp buffer
	  fifowr	:	out std_logic;   --a rising edge on it indicates that a ex_cup reads the ex_fifos
	  fiford	:	out std_logic;   --a rising edge on it indicates that a ex_cup writes the ex_fifos
	  slrd		:	out std_logic;   --reads the endpoint fifo
	  slwr		:	out std_logic;   --writes the endpoint fifo
	  pa2		:	out std_logic;   --the sloe pin
	  pa3		:	in std_logic;   --PA.3 pin
	  pa4		:	out std_logic;   --PA.4 pin
	  pa5		:	out std_logic;   --PA.5 pin 
	  pa6		:	out std_logic;   --PA.6 pin
	  pa7		:	out std_logic;   --PA.7 pin
	  rstfifo	:	out std_logic;
	  pa_in		:	in  std_logic_vector(1 downto 0);  --PA.0 and PA.1 pin
	  Uflag		:	in  std_logic_vector(2 downto 0);  --usb status flags
	  addr		:	out std_logic_vector(3 downto 0)   --multiplexer controlling pin
	  );
end ctr;
architecture behavior of ctr is
  signal start_up : std_logic;   -- the internal globle startting signal
  signal temp     : std_logic_vector(2 downto 0);
 -- signal inter_clk : std_logic;  -- the internal clk
 -- signal temp :    std_logic;
begin
--
  temp <= pa3&pa_in;
  pa2 <= '1';
  pa4 <= '0';
  pa5 <= '1';
  pa6 <= '1';  
  pa7 <= '0';      --cs pin
  fifowr <= busy;  --write the data in ex_fifo when conversion was finished

-- slwr <= busy;
--for endport the input
  process (temp)
  begin
    if temp = "001" then
       ctr <= '1';
    else
       ctr <= '0';
    end if;
  end process;
--for start AD
  process (temp)
  begin
    if temp= "010" then    --busy = '1' then   
       start_up <= '1';
    else
       start_up <= '0';
    end if;
  end process;
--Error light
  process(temp)
  begin
    if temp = "011" then
      led2 <= '0'; 
    else
      led2 <= '1';  
    end if;
  end process; 
--reset fifo
  process(temp)
  begin
    if temp = "100" then
      rstfifo <= '0'; 
    else
      rstfifo <= '1';  
    end if;
  end process;  
--for AD conversion
  process (reset,clk)
    variable counter16 : integer range 0 to 32 := 0;
    variable counter64 : integer range 0 to 128 := 0;
  begin
    if reset = '0' then  -- reset the signals
       addr <= "0001";
       led1 <= '1';
       r_c <= '1';
    elsif clk'event and clk = '1' then
       if start_up = '1' then
	     led1 <= '0';     --indecates the conversion beginning 
         counter64 := counter64 + 1;
         if counter64 = 120 then
           r_c <= '0';    --a falling edge on it indicates a new conversion is startting
         elsif counter64 = 128 then
           counter64 := 0;
           counter16 := counter16 + 1;
           if counter16 = 1 then
             addr <= "0001";     --channal1 I
           elsif counter16 = 2 then
             addr <= "0010";     --channal2 II
           elsif counter16 = 3 then
             addr <= "0011";     --channal3 III
           elsif counter16 = 4 then
             addr <= "1101";     --channal4 avR
           elsif counter16 = 5 then
             addr <= "1111";     --channal5 avL
           elsif counter16 = 6 then
             addr <= "1001";     --channal6 avF
           elsif counter16 = 7 then
             addr <= "0011";     --channal7 C1
           elsif counter16 = 8 then
             addr <= "1110";     --channal8 C2
           elsif counter16 = 9 then
             addr <= "1100";     --channal9 C3
           elsif counter16 = 10 then
             addr <= "1010";     --channal10 C4
           elsif counter16 = 11 then
             addr <= "1000";     --channal11 C5
           elsif counter16 = 12 then
             addr <= "0101";     --channal12 C6
           elsif counter16 = 13 then
             addr <= "0110";     --channal13 X
           elsif counter16 = 14 then
             addr <= "0100";     --channal14 Y
           elsif counter16 = 15 then
             addr <= "0000";     --channal15 Z
           elsif counter16 = 16 then
             addr <= "0111";     --channal16 GND
             counter16 := 0;
           end if; 
         else
           r_c <= '1';
         end if;
      else
         addr <="0001";
         counter16 := 0;
         counter64 := 0;
         led1 <= '1'; 
         r_c <= '1';
      end if;
    end if;  
  end process;
--for exchange the data
  process(clk)  
    variable q : integer  range 0 to 3 :=0;  
  begin
    if clk'event and clk = '1' then
      if empty = '1' and uflag(1)= '1' then
         q := q + 1;
         if q = 1 then
           fiford <= '0';
           slwr <= '0';
         elsif q =2 then
		   q := 0; 
		   fiford <= '1';
           slwr <= '1'; 
		 else
		   q := 0; 
		 end if;
      else
        fiford <= '1';
        slwr <= '1';
      end if;
    end if;
  end process;
end behavior;