代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/403296/11519637
vhd duanxu.vhd
--断续波
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity duanxu is
port(clk:in std_logic;
outp:out integer range 0 to 10
www.eeworm.com/read/403296/11519643
vhd jiu.vhd
--揪 (脉冲宽度由窄变宽，脉冲组的间隔由长变短)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jiu is
port(clk:in std_logic;
outp:out inte
www.eeworm.com/read/403296/11519759
vhd fp.vhd
--分频模块,改变N值,可以得到不同频率的时钟
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
GENERIC (N:integer:=2500);
PORT(clk:IN STD_LOGIC
www.eeworm.com/read/403292/11519853
qmsg frequency.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/403292/11519988
vhd fp.vhd
--分频模块,改变N值,可以得到不同频率的时钟
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
GENERIC (N:integer);
PORT(clk:IN STD_LOGIC;--全局时
www.eeworm.com/read/402196/11541141
c processimage.c
#include
#include
#include
int main(int argc,char *argv[],char **environ)
{
int i;
printf("I am a process image!\n");
printf("My pid = %d, parentpid =
www.eeworm.com/read/402196/11541152
c fork3.c
#include
#include
#include
int main(void)
{
pid_t pid;
pid = fork();
switch(pid) {
case 0:
while(1)
{
printf("A background process, PI
www.eeworm.com/read/402196/11541153
c diffork.c
#include
#include
#include
int globVar = 5;
int main(void)
{
pid_t pid;
int var = 1, i;
printf("fork is diffirent with vfrok \n");
pid = fo
www.eeworm.com/read/402018/11543893
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector
www.eeworm.com/read/402018/11543915
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector