📄 fp.vhd
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--分频模块,改变N值,可以得到不同频率的时钟
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp IS
GENERIC (N:integer);
PORT(clk:IN STD_LOGIC;--全局时钟,25M
clkout:OUT STD_LOGIC);
END fp;
ARCHITECTURE rtl OF fp IS
signal count:integer range 0 to N-1;
signal clkout1:std_logic;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(count=N-1)then
count<=0;
else
count<=count+1;
end if;
end if;
end process;
process(clk,count)
begin
if(clk'event and clk='1') then
if (count<(integer(N/2))) then
clkout1<='0';
else
clkout1<='1';
end if;
end if;
end process;
clkout<=clkout1;
end rtl;
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