fp.vhd

波形发生器之疏密波的产生

--分频模块,改变N值,可以得到不同频率的时钟
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fp IS
GENERIC (N:integer:=2500);
PORT(clk:IN STD_LOGIC;--全局时钟,25M
    outp:out STD_LOGIC);
END fp;

ARCHITECTURE rtl OF fp IS
signal count:integer range 0 to N-1;--2499
begin

 process(clk)
 begin 
	if(clk'event and clk='1') then
	if(count=N-1)then
			count<=0;
	else	
			count<=count+1;
		if (count<(integer(N/2))) then--1250
			outp<='0';
		else
			outp<='1';
		end if;
	end if;
	end if;
end process;
end rtl;