代码搜索：Process
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www.eeworm.com/read/408728/11375579
rpt pci.map.rpt
Analysis & Synthesis report for PCI
Thu Jan 15 18:21:20 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
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1
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vhd ps2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ps2 is
port(sysclk,reset,kbclk,kbdata:in std_logic;
pdata:out std_logic_vector(7 downto 0);
parity:out std_logic;
dtoe :buffer st
www.eeworm.com/read/262892/11386765
h personprocessor.h
/**
* PersonProcessor - Retrieves the bot's name (shortcut)
*
* @author Jonathan Roewen
*/
#ifndef PERSON_PROCESSOR_H
#define PERSON_PROCESSOR_H
#include "AimlProcessor.h"
#include "Subs
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cpp templateprocessor.cpp
/**
* TemplateProcessor - The big dude on campus
*
* @author Jonathan Roewen
*/
#include "TemplateProcessor.h"
#include "Responder.h"
#include "Handler.h"
#include
using name
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h ircprocessor.h
/**
* IrcProcessor - Configures and connects to IRC
*
* @author Jonathan Roewen
*/
#ifndef IRC_PROCESSOR_H
#define IRC_PROCESSOR_H
#include "AimlProcessor.h"
#include "IrcResponder.h"
#
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vhd key.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY key IS
PORT(
clk,k : IN STD_LOGIC;
en : OUT STD_LOGIC
);
END key;
ARCHITECTURE one OF ke
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vhd cnt10.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY cnt10 IS
PORT(
clk,clr,en : IN STD_LOGIC;
q : buffer STD_LOGIC_VECTOR(3 downto 0);
c10
www.eeworm.com/read/408235/11401141
exports posix.exports
##sys#interrupt-hook
##sys#posix-error
##sys#process
##sys#process-wait
##sys#shell-command
##sys#shell-command-arguments
##sys#standard-input
##sys#standard-output
_exit
call-with-input-pipe
call-wit
www.eeworm.com/read/407960/11407010
vhd dffsrst.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl
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vhd dffif.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of