dffsrst.vhd

来自「一部分简单时序逻辑电路的VHDL源代码」· VHDL 代码 · 共 27 行

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is port (
    d: in std_logic;
    clk: in std_logic;
    srst : in std_logic;
    q: out std_logic
    );
end DFF;

architecture rtl of DFF is

begin

  process (clk) begin
    if clk'event and clk = '1' then
      if srst = '1' then
	q <= '0';
      else
        q <= d;
      end if;
    end if;
  end process;

end rtl;