📄 ps2.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity ps2 is
port(sysclk,reset,kbclk,kbdata:in std_logic;
pdata:out std_logic_vector(7 downto 0);
parity:out std_logic;
dtoe :buffer std_logic);
end ps2;
architecture cyclone of ps2 is
signal costate:std_logic_vector(1 downto 0);
signal spdata:std_logic_vector(8 downto 0);
signal start,swto02,recven:std_logic;
signal cnt8:integer range 0 to 15;
begin
str1: process(reset,kbclk,kbdata,start,costate)
begin
if reset = '1' then start <='0';
elsif kbclk'event and kbclk='0'
then if costate = "00" and kbdata = '0' then
start<='1';
end if;
end if;
end process;
str2: process(reset,kbclk,kbdata,start,costate)
begin
if reset = '1' then swto02 <='0';
elsif kbclk'event and kbclk='1'
then if costate = "00" and start = '1' and kbdata='0'
then swto02<='1';
end if;
end if;
end process;
chste: process(reset,sysclk,costate,swto02)
begin
if reset = '1' then costate <= "00";
elsif sysclk'event and sysclk = '1'
then if swto02 = '1' then costate<="01";
elsif cnt8 = 9 then costate <="10";
end if;
end if;
end process;
recv: process(reset,kbclk,kbdata,costate)
begin
if reset ='1'
then cnt8 <= 0;
spdata<="000000000";
elsif kbclk'event and kbclk = '0'
then if costate="01"
then if cnt8 /= 9
then spdata(7 downto 0) <= spdata(8 downto 1);
spdata(8) <= kbdata;
cnt8 <= cnt8 +1;
end if;
end if;
end if;
end process;
rxde: process(reset,kbclk,recven,costate)
begin
if reset = '1' then dtoe <= '0';
elsif kbclk'event and kbclk ='1'
then if cnt8 = 9 and costate = "01" then dtoe <= '1';
end if;
end if;
end process;
parity <= spdata(8);
pdata <= spdata(7 downto 0);
end;
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