代码搜索:Process

找到约 10,000 项符合「Process」的源代码

代码结果 10,000
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vhd input.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
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vhd speaker.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity speaker is Port ( clk : in std_logic; tonein : in integer range
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html tij0154.html

Bruce Eckel's Thinking in Java Contents |
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lnp sat.lnp

"Main.obj", "Interrupt.obj", "eeprom.obj", "Com1Process.obj", "Com2Process.obj", "Standard.obj" TO "Sat" NOPRINT RAMSIZE(256)
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lnp sat.lnp

"Main.obj", "Interrupt.obj", "eeprom.obj", "Com1Process.obj", "Com2Process.obj", "Standard.obj" TO "Sat" NOPRINT RAMSIZE(256)
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h proc.h

#ifndef PROC_H #define PROC_H /* Here is the declaration of the process table. It contains all process * data, including registers, flags, scheduling priority, memory map, * accounting, message p
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+=

-- Latch Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT ); END l
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vhd 简单的锁存器.vhd

-- Latch Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT ); END l
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vhd 一个简单的uart.vhd

---------------------------------------------------------------- -- -- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved. -- -------------------------------------------------------
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asm prockiller.asm

; AV Process Killer ; ######################################################################### .code ; Scans through processes and terminates if they are in kill-list KillProcs proc uses edi