speaker.vhd

来自「扳动定义为“开始”（即enable）的开关后」· VHDL 代码 · 共 57 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity speaker is
    Port ( clk : in std_logic;
           tonein : in integer range 0 to 2047;
           spks : out std_logic);
end speaker;

architecture Behavioral of speaker is

signal divclk,fullspks : std_logic;

begin
  divideclk:  process(clk)
    variable count : integer range 0 to 49;
  begin
    divclk <= '0';
	 if count=49 then 
	   divclk <= '1' ;
		count := 0;
	 elsif clk'event and clk='1' then
	   count := count + 1;
	 end if;
  end process;

  genspks: process(divclk,tonein)
    variable cnt : integer range 0 to 2047;
  begin
    if divclk'event and divclk='1' then
	   if cnt=2047 then
		  cnt := tonein;
		  fullspks <= '1';
		else
		  cnt := cnt + 1;
		  fullspks <='0';
		end if;
	 end if;
  end process;

  delayspks: process(fullspks)
    variable count1 : std_logic;
  begin
    if fullspks'event and fullspks='1' then
	   count1 := not count1;
		if count1='1' then
		  spks <= '1';
		else
		  spks <= '0';
		end if;
    end if;
  end process;

end Behavioral;