control.vhd

来自「扳动定义为“开始”（即enable）的开关后」· VHDL 代码 · 共 64 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity control is
    port(start:in std_logic;
	      a:in std_logic;
			b:in std_logic;
			c:in std_logic;
			d:in std_logic;
			clk:in std_logic;
			spkout:out std_logic;
			index:buffer std_logic_vector(5 downto 0)
         );
end control;

architecture Behavioral of control is
--signal code : std_logic_vector(1 downto 0);
signal tonetmp : integer range 0 to 2047;
--signal index1:std_logic_vector(1 downto 0);

component tone is
    Port ( index : in std_logic_vector(5 downto 0);
           --code : out std_logic_vector(1 downto 0);
           tone_out : out integer range 0 to 2047);
end component;

component speaker is
    Port ( clk : in std_logic;
           tonein : in integer range 0 to 2047;
           spks : out std_logic);
end component;

begin
process(start,a,b,c,d)
begin
     if(start='0') then
	     if(a='0' or b='0' or c='0' or d='0')	then
		     index<="111110";
        else
			  index<="111111";
        end if;
     elsif(start='1')  then
	     if(a='0' or b='0' or c='0' or d='0')	then
		     index<="111011";
        else
			  index<="111111";
        end if;
     else
	     index<="111111";
	  end if;
end process;
--index<=index1;
U1: tone port map (index,tonetmp);
U2: speaker port map (clk,tonetmp,spkout);

end Behavioral;