input.vhd

扳动定义为“开始”（即enable）的开关后

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity input is
    port(--en:in std_logic;
	      clk:in std_logic;
			--reset:in std_logic;
			a:in std_logic;
			b:in std_logic;
			c:in std_logic;
			d:in std_logic;
			output:out std_logic_vector(3 downto 0);
			flag:out std_logic
			);
end input;

architecture Behavioral of input is
signal flagf:std_logic;
begin
     input:process(clk,a,b,c,d)
	  begin
	  if (clk'event and clk='1') then
	       --if(en='1') then flagf<='0';
			 --end if;
			-- if(en='0') then
			    if   (a='0') then flagf<='1';output<="0001";
				 elsif(b='0') then flagf<='1';output<="0010";
				 elsif(c='0') then flagf<='1';output<="0100";
			    elsif(d='0') then flagf<='1';output<="1000";
				 --else
				 --output<="0000";
				 end if;
          --end if;
     end if;
end process;

--process(clk,reset)
--begin
    --if(clk'event and clk='1') then
	    --if(reset='0')	then
		   --flag<='0';
			--led<="11111111";
       --end if;
    --end if;
--end process;

	flag<=flagf;
end Behavioral;