代码搜索：Process
找到约 10,000 项符合「Process」的源代码
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www.eeworm.com/read/453878/7406235
plg lcd12232.plg
礦ision2 Build Log
Project:
F:\windows\程序\例33-LCD12864\LCD12864.uv2
Project File Date: 08/26/2008
Output:
Build target 'Target 1'
compiling lc
www.eeworm.com/read/453698/7414315
vhd clk_div.vhd
--DDS时钟为448KHZ，周期为 ，一系统时钟为基准，14个状态为一个循环产生各种时钟信号clk_DDS
library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
port(
c1_1024:in std_logic;
c2_DDS:in std_logic;
clk500,clk1000:out std
www.eeworm.com/read/453496/7418565
c execl.c
#include
#include
void main(void)
{
printf("About to call child process\n\n");
execl("CHILD.EXE", "CHILD.EXE",
"AAA", "BBB", "CCC", NULL);
printf("\n\nBa
www.eeworm.com/read/453446/7420384
vhd vhdl code1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY comp4b IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);
END ENTITY;
ARCHITECTURE behav OF comp4b IS
BEGIN
PROCESS(A,B)
BEGIN
IF(
www.eeworm.com/read/453446/7420424
log console.log
Design: 9:20 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\dff\dff.adf"
Design: Error: C:\My Designs\dff\src\VHDL code4.vhd cannot be compiled.
Compilation...
File: .\src\VHDL
www.eeworm.com/read/453446/7420487
log console.log
Design: 8:39 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\halfadder\halfadder.adf"
Design: Error: C:\My Designs\halfadder\src\VHDL code6.vhd cannot be compiled.
Compilation...
www.eeworm.com/read/453446/7420502
log console.log
Design: 1:45 PM, Sunday, April 12, 2009
Design: Opening design "C:\My Designs\tff\tff.adf"
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
www.eeworm.com/read/453446/7420515
bak vhdl code5.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1'
www.eeworm.com/read/453134/7425993
ned tictoc2.ned
//
// This file is part of an OMNeT++/OMNEST simulation example.
//
// Copyright (C) 2003 Ahmet Sekercioglu
// Copyright (C) 2003-2005 Andras Varga
//
// This file is distributed WITHOUT ANY WAR
www.eeworm.com/read/453127/7426079
plg lcd1602.plg
礦ision2 Build Log
Project:
G:\软件备份\Proteus 6.7\JJJ仿真电路\字符液晶1602\Keil\LCD1602.uv2
Project File Date: 09/18/2005
Output:
Build target 'Target 1'