console.log

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

Design: 8:39 PM, Tuesday, March 31, 2009
Design: Opening design "c:\my designs\halfadder\halfadder.adf"
Design: Error: C:\My Designs\halfadder\src\VHDL code6.vhd cannot be compiled.
Compilation...
File: .\src\VHDL code6.vhd
Compile Entity "HA"
Compile Architecture "struct" of Entity "HA"
Warning: ELAB1_0026: VHDL code6.vhd : (11, 0): There is no default binding for component "myXOR".
Compile success 0 Errors 1 Warnings  Analysis time :  0.0 [s]
ELBREAD: Elaboration process.
ELBREAD: Warning: Component X1 : myXOR not bound.
ELBREAD: Elaboration time 0.0 [s].
KERNEL: Main thread initiated.
KERNEL: Kernel process initialization phase.
ELAB2: Elaboration final pass...
ELAB2: Elaboration final pass complete - time: 0.0 [s].
KERNEL: Kernel process initialization done.
8:39 PM, Tuesday, March 31, 2009
Simulation has been initialized
Selected Top-Level: HA (struct)
Simulation has been stopped