代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/349603/10814331
plg dia222222.plg
礦ision3 Build Log
Project:
C:\Documents and Settings\Administrator\桌面\课题2 电子钟\dia222222.uv2
Project File Date: 08/21/2008
Output:
Build target
www.eeworm.com/read/349548/10819277
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector
www.eeworm.com/read/349548/10819333
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector
www.eeworm.com/read/349548/10819417
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/349548/10819437
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/349548/10819441
vhd fredivn1.vhd
--odd frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn1 is
GENERIC (N:integer:=15);
port (clk:in
www.eeworm.com/read/349548/10819455
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/349548/10819822
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/349501/10823233
vhd pwm.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity pwm is
port (clk: in std_logic;
q : out std_logic
);
end pwm;
architecture lxf of pwm is
www.eeworm.com/read/349500/10823512
vhd switch.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity switch is
port(
led1,led2,led3,led4 : out std_logic;
key1,key2,key3,key4 : in std_l