pwm.vhd

来自「通过改变pwm的占空比」· VHDL 代码 · 共 53 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity pwm is
port (clk: in std_logic;
          q : out std_logic
     );
end pwm;

architecture lxf of pwm is 

signal b:std_logic_vector(7 downto 0);
signal c,m,qq:std_logic;
signal v:std_logic_vector(7 downto 0);
signal count :   integer range 0 to 2500;
signal count1:   integer range 0 to 150;
signal clk1:  std_logic;
begin

process(clk) --system clock fenpin
begin
if(clk 'event and clk='1')then
   if(count<2500)then count<=count+1;
     else count<=0;clk1<=not clk1;
   end if;
end if;
end process;

process(clk1)  
begin
if(clk1 'event and clk1='1')then
   if(count1<150)then count1<=count1+1;
     else v<=v+1;count1<=0;
   end if;
end if;
end process;

process(clk)
begin
    if clk 'event and clk='1' then
    b<= b-1; 
    end if ;
end process;

c<='1' when v > b 
       else '0' ;
m<='1' when v = "11111111" 
       else '0' ;
qq<= c or m;
q<=qq;
end lxf;