counter24.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册 》源代码」· VHDL 代码 · 共 40 行

--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
 port(clk:in std_logic;
      bcd1:out std_logic_vector(3 downto 0);
      bcd2:out std_logic_vector(3 downto 0));
end counter24;

architecture rtl of counter24 is
 signal bcd1n:std_logic_vector(3 downto 0):="0000";
 signal bcd2n:std_logic_vector(3 downto 0):="0000";
 begin
 bcd1<=bcd1n;
 bcd2<=bcd2n;
     process(clk)
    begin
     if(clk'event and clk='0') then
       if((bcd1n="1001" and bcd2n<="0001") or (bcd1n="0011" and bcd2n="0010")) then
          bcd1n<="0000";
       else         
        bcd1n<=bcd1n+1; 
      end if;
     end if;
end process;
 process(clk)
   begin
     if(clk'event and clk='0') then
       if(bcd1n="1001" and bcd2n<="0001") then
          bcd2n<=bcd2n+1;
       elsif(bcd1n="0011" and bcd2n="0010") then
           bcd2n<="0000";
       end if;
     end if;
end process;
end rtl;