代码搜索:Packet
找到约 10,000 项符合「Packet」的源代码
代码结果 10,000
www.eeworm.com/read/427598/8931487
h packet_out.h
/***************************************************************************
packet_out.h - description
-------------------
begin
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vho packet_cache.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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veo packet_cache.veo
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
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xcp packet_cache.xcp
# Xilinx CORE Generator 6.3.03i
SELECT Dual_Port_Block_Memory Spartan3 Xilinx,_Inc. 6.1
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port
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xco packet_cache.xco
# Xilinx CORE Generator 6.3.03i
# Username = winwalk
# COREGenPath = D:\Program Files\Xilinx\coregen
# ProjectPath = E:\Documentation\Digital\PROJECT\QAM\MAC\TEST_TRAN\ver1.4
# ExpandedProjectPath
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edn packet_cache.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 7 15 19 14 32)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "X
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sym packet_cache.sym
VERSION 5
BEGIN SYMBOL packet_cache
SYMBOLTYPE BLOCK
TIMESTAMP 2007 7 15 11 14 32
SYMPIN 0 48 Input addra(12:0)
SYMPIN 0 80 Input dina(7:0)
SYMPIN 0 112 Input wea
SYMPIN 0 240 Input clka
SYMPI
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vhd packet_cache.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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v packet_cache.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
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