packet_cache.sym

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

VERSION 5
BEGIN SYMBOL packet_cache
SYMBOLTYPE BLOCK
TIMESTAMP 2007 7 15 11 14 32
SYMPIN 0 48 Input addra(12:0)
SYMPIN 0 80 Input dina(7:0)
SYMPIN 0 112 Input wea
SYMPIN 0 240 Input clka
SYMPIN 0 272 Input addrb(12:0)
SYMPIN 0 464 Input clkb
SYMPIN 288 272 Output doutb(7:0)
RECTANGLE N 32 0 256 496 
BEGIN DISPLAY 36 48 PIN addra(12:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 48 32 48 
END LINE
BEGIN DISPLAY 36 80 PIN dina(7:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 80 32 80 
END LINE
BEGIN DISPLAY 36 112 PIN wea ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 112 32 112 
BEGIN DISPLAY 36 240 PIN clka ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 240 32 240 
BEGIN DISPLAY 36 272 PIN addrb(12:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 272 32 272 
END LINE
BEGIN DISPLAY 36 464 PIN clkb ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 464 32 464 
BEGIN DISPLAY 252 272 PIN doutb(7:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 256 272 288 272 
END LINE
END SYMBOL