代码搜索结果

coolbor工作室——PCB设计（经验文章）——印制线路板高频电路布线技巧

import java.awt.*; import java.io.*; import java.lang.*; import java.util.*; class PCB { int Wmutex; int Rrun; int Wrun; int Rwait; int Wwait; public void display(int Rrun,int Rwait,

#include "stdio.h" #include #include #define get(type) (type*)malloc(sizeof(type)) //分配作业空间 #define NULL 0 typedef struct PCB{ char name; //作业名 char Estate

1: //user.c 2: #include "pic18.h" 3: #include "os\os.h" 4: #include "user\user.h" 5: #include "user\pcb.h" 6: 7: static unsigned char CommRxCnt,CommRxOld;

#include "stdio.h" #include "stdlib.h" #include "string.h" typedef struct node /*创建PCB*/ { char name[10]; /*进程标识*/ int prio; /*进程优先数*/ int cputime; /*进程占用CPU时间*/ int needtime

coolbor工作室——PCB设计（经验文章）——印制线路板高频电路布线技巧

Protel Design System Design Rule Check PCB File : \wangjie\work\book\Exa801\Documents\exa1402.PCBDOC Date : 2005-3-13 Time : 21:22:44 Processing Rule : Short-Circuit Constraint (Allowed=

Protel Design System Design Rule Check PCB File : \wangjie\work\book\new\myexample\1\mypcb.PCBDOC Date : 2005-3-15 Time : 14:55:45 Processing Rule : Clearance Constraint (Gap=8mil) (All)

Layer Pairs Export File for PCB: E:\修改书稿\protel\09源文件\第六章\master\master.PcbDoc LayersSetName=Top_Bot_Thru_Holes|DrillFile=master.txt|LayerPairs=gtl,gbl

(wiring # Wiring file created by Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47 (resolution MIL 1000) # Net A0 (wire (path TOP 6000 -500000 2600000 -500000 2643430 -460000 2683430