mypcb.drc

protel电路设计教程

Protel Design System Design Rule Check
PCB File : \wangjie\work\book\new\myexample\1\mypcb.PCBDOC
Date     : 2005-3-15
Time     : 14:55:45

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=8mil) (Preferred=8mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:01