exa1402.drc

protel电路设计教程

Protel Design System Design Rule Check
PCB File : \wangjie\work\book\Exa801\Documents\exa1402.PCBDOC
Date     : 2005-3-13
Time     : 21:22:44

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:07