代码搜索：PATH
找到约 10,000 项符合「PATH」的源代码
代码结果 10,000
www.eeworm.com/read/374904/9379477
dll u32path.dll
www.eeworm.com/read/372885/9488992
v sdr_data_path.v
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
`include "Sdram_Params.h"
input CLK;
www.eeworm.com/read/364326/9912131
doc setting_java_path.doc
www.eeworm.com/read/167001/9986354
c alloc_path_name.c
/* *
* $Id: alloc_path_name.c 176 2005-06-28 14:47:59Z shawill $
*
* This file is part of Fenice
*
* Fenice -- Open Media Server
*
* Copyright (C) 2004 by
*
* - Giampaolo Mancini
www.eeworm.com/read/361281/10061101
v sdr_data_path.v
/******************************************************************************
*
* LOGIC CORE: SDR Data Path Module
* MODULE NAME: sdr_data_path()
* COMPANY: No
www.eeworm.com/read/359197/10161746
v ddr_data_path.v
/******************************************************************************
*
* LOGIC CORE: DDR Data Path Module
* MODULE NAME: ddr_data_path()
* COMPANY:
www.eeworm.com/read/359197/10161789
tlg ddr_data_path.tlg
Selecting top level module ddr_sdram
Synthesizing module pll1
Synthesizing module ddr_control_interface
Synthesizing module ddr_command
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\sy
www.eeworm.com/read/359197/10161800
xrf ddr_data_path.xrf
vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v, synplify
source_file = 2, d:\projects\alter
www.eeworm.com/read/359197/10161803
srs ddr_data_path.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 5.3.0 from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sat May 20 12:17:
www.eeworm.com/read/359197/10161809
srm ddr_data_path.srm
f "noname"; #file 0
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v"; #file 1
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; #file 2