代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/418802/10895674
txt counter.txt
Program
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deton is
port(
clock,reset: in std_logic;
p1: in std_logic_vector(3 downto 0);
digit1,digit2: out st
www.eeworm.com/read/170130/7102967
ant testwave.ant
-- D:\MODEL\LAB3
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Jun 16 15:52:07 2006
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_
www.eeworm.com/read/457446/7325511
vhd lzw_beh.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
entity lzw_beh is
Port ( c
www.eeworm.com/read/441288/7672116
vhd regfile.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--LIBRARY altera_mf;
--USE altera_mf.ALL;
USE work.procmem_defi
www.eeworm.com/read/441288/7672119
bak regfile.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all
use ieee.std_logic_unsigned.all;
--LIBRARY altera_mf;
--USE altera_mf.ALL;
USE work.procmem_defin
www.eeworm.com/read/441060/7676639
vhd cpu_test.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity cpu_test is
end entity cpu_test;
architecture one of cpu_test i
www.eeworm.com/read/436708/7765484
vhd duc.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
-- Uncomm
www.eeworm.com/read/397146/8064804
vhd oc_i2c_master.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--use ieee.numeric_std.all;
ENTITY oc_i2c_master IS
PORT (
scl_pad_io : INOUT
www.eeworm.com/read/332405/12759620
vhd cslt_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
entity rcd_cntr is
port (rcd_end : out std_logic;
Reset : in std_logic;
Clk : in std_logic;
www.eeworm.com/read/332405/12759643
vhd rcd_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
use IEEE.std_logic_unsigned.all;
entity cslt_cntr is
port (cslt_end : out std_logic;
Reset : in std_logic;
Clk : in std_logi