cpu_test.vhd

自己刚写的一个RISC的cpu

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity cpu_test is
end entity cpu_test;

architecture one of cpu_test is

  component cpu1
     port(clk:in std_logic;
          rst:in std_logic;
          memout:in std_logic_vector(15 downto 0);
          ram_in:in std_logic;
          result:out std_logic;
          alu_result:out std_logic;
          re:out std_logic;
          wr:out std_logic;
          pc_address:out std_logic_vector(15 downto 0)
          );
  end component;

  component rom
      port( address:in std_logic_vector(15 downto 0);
            memout:out std_logic_vector(15 downto 0);
        
            re:in std_logic
            );
  end component;
  
  component ram
      port( address:in std_logic_vector(15 downto 0);
            ram_out:out std_logic;
            clk:in std_logic;
            re:in std_logic;
            wr:in std_logic
            );
   end component;
   
   signal clk:std_logic:='0';
   signal rst:std_logic:='1';
   signal memout:std_logic_vector(15 downto 0);
   signal ram_in:std_logic;
   signal result:std_logic;
   signal alu_result:std_logic;
   signal re:std_logic;
   signal wr:std_logic;
   signal pc_address:std_logic_vector(15 downto 0);
   
   begin
   U1:cpu1 port map(
                     clk=>clk,
                     rst=>rst,
                     memout=>memout,
                     ram_in=>ram_in,
                     result=>result,
                     alu_result=>alu_result,
                     re=>re,
                     wr=>wr,
                     pc_address=>pc_address
                     );
  U2:rom port map(
                  address=>pc_address,
                  memout=>memout,
                  re=>re
                 ); 
 U3:ram port map(
                  address=>pc_address,
                  ram_out=>ram_in,
                  clk=>clk,
                  re=>re,
                  wr=>wr
                 ); 
 
 process(clk)
      begin
       clk<=not clk    after 5 ns;
  end process;   
  
  rst<='0' after 10 ns;
   end one;