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Logic Analyzer 的代码
sanjiao.vhd
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
divide.txt
-----------compare
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare2 is
port(q:in std_logic_vector(8 downto 0);
b:in std_logic_vector(7 downto 0);
bbfifo_16x8.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
v_riscmcu.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU projec
encoder.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encoder IS
PORT (e,f,g,h,i,j :IN std_logic;
codeout :OUT std_logic_vector(3 DOWNTO 0)
);
END encoder;
ARCHITECTURE behave
vote7.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vote7 IS
PORT( men:IN STD_LOGIC_VECTOR(6 downto 0);
LedPass,LedFail: OUT STD_LOGIC);
END vote7;
bbfifo_16x8.vhd
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
jishixianshi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JISHIXIANSHI IS
PORT ( CLK0 ,clk1, EN, RST : IN STD_LOGIC;
SG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
mc8051_clockdiv_.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-----------------------------ENTITY DECLARATION--------------------------------
entity mc8051_clockdiv is
port (clk