vote7.vhd

来自「含有七人表决器」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY vote7 IS
      PORT( men:IN STD_LOGIC_VECTOR(6 downto 0);
      LedPass,LedFail: OUT STD_LOGIC);
END  vote7;
ARCHITECTURE behave OF vote7 IS
SIGNAL pass: STD_LOGIC;
BEGIN
    PROCESS(men)
         variable temp:STD_LOGIC_VECTOR(2 downto 0);
       BEGIN
           temp:="000";
           for i in 0 to 6 LOOP
                if(men(i)='1') then
                    temp:=temp+1;
                ELSE 
                   temp:=temp+0;
              END if;
         END LOOP;
         pass<=temp(2);
      END PROCESS;
      LedPass<='1'  WHEN Pass='1' ELSE'0';
      LedFail<='1'  WHEN Pass='0' ELSE'0';
END behave;