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r128x4_25um.vhd
------------------------------------------------------------------------
-- File : r128x4_25um.vhd
-- Design Date: June 9, 1998
-- Creation Date: Mon May 06 13:42:47 2002
-- Created By SpDE Vers
count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_100MS: OUT ST
mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_100MS: OUT ST
mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
mb.vhd
--1.顶层文件：mb.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb is
port (
clk1,clk2: in STD_LOGIC;
clr
dled.vhd
--顶层文件名：mb.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb is
port (
clk1,clk2: in STD_LOGIC; ----引脚定义
dled.vhd
--1,DLED 时钟总模块
--文件名：DLED.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DLED is
port (
clk1,clk2: in
count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN,REBACK: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 D
mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,reback,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);