📄 dled.vhd
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--1,DLED 时钟总模块
--文件名：DLED.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DLED is
port (
clk1,clk2: in STD_LOGIC; ----引脚定义
clr: in STD_LOGIC;
start: in STD_LOGIC;
K1: in STD_LOGIC;
LED_SA: out STD_LOGIC;
LED_SB: out STD_LOGIC;
LED_SC: out STD_LOGIC;
LED_A: out STD_LOGIC;
LED_B: out STD_LOGIC;
LED_C: out STD_LOGIC;
LED_D: out STD_LOGIC;
LED_E: out STD_LOGIC;
LED_F: out STD_LOGIC;
LED_G: out STD_LOGIC;
LED_DP: out STD_LOGIC);
end DLED;
architecture dled_arch of DLED is
COMPONENT j_t
PORT(
k : IN STD_LOGIC ;
up ,down : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT DLEDDIS
PORT(
H10 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
HOUR1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
M10 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
MIN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
SED10 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clk,clr : IN STD_LOGIC;
OUTBCD : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SEG : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT c6
PORT(
clr,start,clk,upin,downin : IN STD_LOGIC;
upout,downout : OUT STD_LOGIC;
daout : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT c10
PORT(
clr,start,clk,upin,downin :IN STD_LOGIC;
upout,downout : out STD_LOGIC;
daout : out std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL k : STD_LOGIC ;
SIGNAL upout0 ,downout0 : STD_LOGIC;
SIGNAL H101 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL HOUR11 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL M101 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL MIN11 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL SED101 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL S11 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL OUTBCD1: STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL SEG1: STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL clk : STD_LOGIC;
SIGNAL upout1, downout1 :STD_LOGIC;
SIGNAL upout2, downout2 :STD_LOGIC;
SIGNAL upout3, downout3 :STD_LOGIC;
SIGNAL upout4, downout4 :STD_LOGIC;
SIGNAL upout5, downout5 :STD_LOGIC;
SIGNAL upout6, downout6 :STD_LOGIC;
SIGNAL upin , downin :STD_LOGIC;
SIGNAL upout, downout :STD_LOGIC;
begin
clk<=clk1;
al: j_t PORT MAP(k1 ,up =>upout0 ,down =>downout0);
Ssl1: c10 PORT MAP(clr=>clr,start=>start ,clk1 , upin=>upout0 ,downin=>downout0 ,upout=>upout1,downout=>downout1,daout=>S11(3 DOWNTO 0)); --10mSECOND LOW
Ssh1: c10 PORT MAP(clr =>clr,start =>start,clk1 , upin=>upout1,downin=>downout1, upout=>upout2, downout=>downout2 ,daout=>SED101(3 DOWNTO 0)); --100mSECOND HIGH
SL2: c10 PORT MAP(clr =>clr,start =>start,clk1 , upin=>upout2,downin=>downout2, upout=>upout3, downout=>downout3 ,daout=>MIN11(3 DOWNTO 0)); --SECOND HIGH
SH2: c6 PORT MAP(clr =>clr,start =>start,clk1 , upin=>upout3,downin=>downout3, upout=>upout4, downout=>downout4 ,daout=>M101(2 DOWNTO 0)); --SECOND HIGH
ML3: c10 PORT MAP(clr =>clr,start =>start,clk1 , upin=>upout4,downin=>downout4, upout=>upout5, downout=>downout5 ,daout=>HOUR11(3 DOWNTO 0)); --MINUTE LOW
MH3: c6 PORT MAP(clr =>clr,start =>start,clk1 , upin=>upout5,downin=>downout5, upout=>upout6, downout=>downout6 ,daout=>H101(2 DOWNTO 0)); --MINUTE HIGH
DISPLAY: DLEDDIS PORT MAP(H10=>H101,HOUR1=>HOUR11,M10=>M101,MIN1=>MIN11,SED10=>SED101,S1=>S11,clk =>CLK2,clr=>clr,OUTBCD=>OUTBCD1,SEG=>SEG1);
LED_SA <= SEG1(0);
LED_SB <= SEG1(1);
LED_SC <= SEG1(2);
LED_A <= OUTBCD1(0);
LED_B <= OUTBCD1(1);
LED_C <= OUTBCD1(2);
LED_D <= OUTBCD1(3);
LED_E <= OUTBCD1(4);
LED_F <= OUTBCD1(5);
LED_G <= OUTBCD1(6);
LED_DP <= '0';
end dled_arch;
--2.十进制可逆计数器代码：
--原理为加法计数器，计数十时由cout进位
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c10 is
port(clr,start,clk,upin,downin: IN STD_LOGIC;
upout,downout: out STD_LOGIC;
daout: out std_logic_vector(3 downto 0));
end c10;
architecture a of c10 is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,clr,upin,start,downin)
begin
if clr='1' then
temp<="0000";
elsif (clk'event and clk='1') then
if start='1' then
if (upin='1' and downin='0') then
if( temp="1001") then temp<="0000";
Else temp<=temp+1;
End if;
elsif (upin='0' and downin='1')then
if( temp="0000") then temp<="1001";
Else temp<=temp-1;
end if;
end if;
end if;
end if;
end process;
upout<= '1'when(upin='1' and downin='0'and temp="1001")else'0';
downout <='1'when(upin='0' and downin='1'and temp="0000")else'0';
daout<=temp;
end a;
--3,六进制可逆计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c6 is
port(clr,start,clk,upin,downin: in STD_LOGIC;
upout,downout: out STD_LOGIC;
daout: out std_logic_vector(2 downto 0));
end c6;
architecture a of c6 is
signal temp:std_logic_vector( 2 downto 0);
begin
process(clk,clr,upin,start,downin)
begin
if clr='1' then
temp<="000";
elsif (clk'event and clk='1') then
if start='1' then
if (upin='1' and downin='0') then
if( temp="101") then temp<="000";
Else temp<=temp+1;
End if;
elsif (upin='0' and downin='1')then
if( temp="000") then temp<="101";
Else temp<=temp-1;
end if;
end if;
end if;
end if;
end process;
upout<= '1'when(upin='1' and downin='0'and temp="101")else'0';
downout <='1'when(upin='0' and downin='1'and temp="000")else'0';
daout<=temp;
end a;
--4. 数码管动态扫描显示模块
--文件名：DLEDDIS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DLEDDIS IS
PORT(
H10 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
HOUR1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
M10 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
MIN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
SED10 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ClK : IN STD_LOGIC;
clr : IN STD_LOGIC;
OUTBCD : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SEG : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END DLEDDIS;
--*******************************************************
ARCHITECTURE DLEDDIS_ARCH OF DLEDDIS IS
SIGNAL NUM : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL COUNT: STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
PROCESS (ClK)
BEGIN
if (clr='1') then
COUNT <= "000";
elsIF ClK'event AND ClK = '1' THEN
if (COUNT=5) then COUNT<="000";
else COUNT<=COUNT + 1;
end if;
END IF;
END PROCESS;
SEG <= COUNT;
NUM <= S1 WHEN COUNT = 0 ELSE
SED10 WHEN COUNT = 1 ELSE
MIN1 WHEN COUNT = 2 ELSE
M10 WHEN COUNT = 3 ELSE
HOUR1 WHEN COUNT = 4 ELSE
H10;
--pgfedcba
OUTBCD <= "0111111" WHEN NUM = 0 ELSE
"0000110" WHEN NUM = 1 ELSE
"1011011" WHEN NUM = 2 ELSE
"1001111" WHEN NUM = 3 ELSE
"1100110" WHEN NUM = 4 ELSE
"1101101" WHEN NUM = 5 ELSE
"1111101" WHEN NUM = 6 ELSE
"0000111" WHEN NUM = 7 ELSE
"1111111" WHEN NUM = 8 ELSE
"1101111" WHEN NUM = 9 ELSE
"1110111" WHEN NUM = 10 ELSE
"1111100" WHEN NUM = 11 ELSE
"0111001" WHEN NUM = 12 ELSE
"1011110" WHEN NUM = 13 ELSE
"1111001" WHEN NUM = 14 ELSE
"1110001" WHEN NUM = 15 ELSE
"0000000";
END DLEDDIS_ARCH;
--------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY j_t IS
PORT(
k : IN STD_LOGIC ;
up ,down : OUT STD_LOGIC
);
END j_t;
--*******************************************************
ARCHITECTURE a OF j_t IS
BEGIN
PROCESS
BEGIN
if (k='1') then
up <='1';down<='0';
elsIF( k='0')THEN
up <='0';down <='1';
END IF;
END PROCESS;
END a;
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