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library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity set is port(reset:in std_logic; number10:in std_logic_vector(3 downto 0)

library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity set is port(reset:in std_logic; number10:in std_logic_vector(3 downto 0)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity multi8x8 is port(clk, start: in std_logic; a, b: in std_logic_vector(7 downto 0); ariend: out std_logic;

电子钟vVHDL程序 1.10进制计数器设计与仿真 ---文件名：counter10.vhd。 ---功能：10进制计数器，有进位c library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter10 i

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned."+"; entity opt is port (reset:in std_logic; in1:in std_logic_vector(15 downto 0); in2:in std_Logic_vector(31 d

-- Altera Microperipheral Reference Design Version 0802 -------------------------------------------------------------------------------- -- File Name: l_conversions_p.vhd -------------------------

-- -- --------------------------------------------------------------------------------------- -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 --

--REG1.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG1 IS PORT(D: IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END ENTITY

--REG2.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG2 IS PORT(D: IN STD_LOGIC_VECTOR(8 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END ENTITY

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