set.vhd

我的课程设计

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity set is
 port(reset:in std_logic;
      number10:in std_logic_vector(3 downto 0);
      number01:in std_logic_vector(3 downto 0);
      time10:out std_logic_vector(3 downto 0);
      time01:out std_logic_vector(3 downto 0));
end set;

architecture behave of set is

 begin
   process(reset,number10,number01)
   begin
if(reset='0')then
       time10 <=number10;
       time01 <=number01;
       
   else
       null;
   end if;
 end process;
end behave;