songbaoli.txt

数字逻辑电子钟课程设计报告源代码简单明了

 电子钟vVHDL程序
1.10进制计数器设计与仿真
---文件名：counter10.vhd。
---功能：10进制计数器，有进位c
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
    port(clk:in std_logic;
         reset:in std_logic;
         din:in std_logic_vector(3 downto 0);
         dout:out std_logic_vector(3 downto 0);
         c:out std_logic);
end counter10 ;
architecture behav of counter10 is
   signal cout:std_logic_vector(3 downto 0);
begin
  dout<=cout;
process(clk,reset,din)
  begin
    if reset='0'then
      cout<=din;
      c<='0';
    elsif rising_edge(clk)then
       if cout="1001"then
          cout<="0000";
          c<='1';
       else
          cout<=cout+1;
          c<='0';
       end if;
    end if;
end process;
end behav;
2.6进制计数器设计与仿真
---文件名：counter6.vhd。
---功能：6进制计数器，有进位c
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter6 is
    port(clk:in std_logic;
         reset:in std_logic;
         din:in std_logic_vector(2 downto 0);
         dout:out std_logic_vector(2downto 0);
         c:out std_logic);
end counter6 ;
architecture behav of counter6 is
   signal cout:std_logic_vector(2 downto 0);
begin
  dout<=cout;
process(clk,reset,din)
  begin
    if reset='0'then
      cout<=din;
      c<='0';
    elsif rising_edge(clk)then
       if cout="101"then
          cout<="000";
          c<='1';
       else
          cout<=cout+1;
          c<='0';
       end if;
    end if;
end process;
end behav;
3.24进制计数器设计与仿真
---文件名：counter24.vhd。
---功能：24进制计数器，有进位c
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
    port(clk:in std_logic;
         reset:in std_logic;
         din:in std_logic_vector(5 downto 0);
         dout:out std_logic_vector(5 downto 0));
        
end counter24 ;
architecture behav of counter24 is
   signal cout:std_logic_vector(5 downto 0);
begin
  dout<=cout;
process(clk,reset,din)
  begin
    if reset='0'then
      cout<=din;
    elsif rising_edge(clk)then
       if cout(3 downto 0)="1001"then
          cout(3 downto 0)<="0000";
          cout(5 downto 4)<=cout(5 downto 4)+1;
       else
          cout(3 downto 0)<=cout(3 downto 0)+1;
       end if;
       if count="100011"then
          count<="000000";
       end if;
     end if;
end process;
end behav;
4.译码器设计
————文件名：decoder.vhd
————将4bit二进制数译码在led上显示相应数字。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
   port( din:in std_logic_vector(3 downto 0);四位二进制码输入
         dout:out std_logic_vector(6 downto 0));输出led七段码
end decoder;
architecture behav of decoder is
begin
process(din)
   begin
      case din is
         when"0000"=>dout<="0000001";--0
         when"0001"=>dout<="0000001";--1
         when"0010"=>dout<="0000001";--2
         when"0011"=>dout<="0000001";--3
         when"0100"=>dout<="0000001";--4
         when"0101"=>dout<="0000001";--5
         when"0110"=>dout<="0000001";--6
         when"0111"=>dout<="0000001";--7
         when"1000"=>dout<="0000001";--8
         when"1001"=>dout<="0000001";--9
         when others=>dout<="1111111";
      end case;
end process;
end behav;
5.顶层设计与仿真
————文件名：clok.vhd.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock is
   port(clk:in std_logic;--1Hz
        reset:in std_logic:--复位信号
        dins:in std_logic_vector(6 downto 0);--秒钟预置
        dinm:in std_logic_vector(6 downto 0);--分钟预置
        dinh:in std_logic_vector(6 downto 0);--时钟预置
        secondl:out std_logic_vector(6 downto 0);--秒钟低位输出
        secondh:out std_logic_vector(6 downto 0);--秒钟高位输出
        minutel:out std_logic_vector(6 downto 0);--分钟低位输出
        minuteh:out std_logic_vector(6 downto 0);--分钟高位输出
        hourl:out std_logic_vector(6 downto 0);--时钟低位输出
        hourh:out std_logic_vector(6 downto 0);--时钟高位输出
end clock;
architecture behav of clock is
component 10 is
  port(clk:in std_logic;
     reset:in std_logic;
     din:in std_logic_vector(3 downto 0);
     dout:out std_logic_vector(3 downto 0);
     c:out std_logic);
end component;
component 6 is
   port(clk:in std_logic;
      reset:in std_logic;
      din:in std_logic_vector(2 downto 0);
      dout:out std_logic_vector(2downto 0);
      c:out std_logic);
end component;
component 24 is
    port(clk:in std_logic;
         reset:in std_logic;
         din:in std_logic_vector(5 downto 0);
         dout:out std_logic_vector(5 downto 0));
end component;
component decoder is
    port( din:in std_logic_vector(3 downto 0);
         dout:out std_logic_vector(6 downto 0));
end component;


signal c1,c2,c3,c4:std_logic;
signal doutsl,doutml:std_logic_vector_(3 downto 0);
signal doutsh,doutmh:std_logic_vector_(2 downto 0);
signal douth:std_logic_vector(5 downto 0);
signal rdoutsh,rdoutmh:std_logic_vector_(3 downto 0);
signal rdouth:std_logic_vector(7 downto 0);
begin
rdoutsh<='0'&doutsh;--将秒的高位数据变为4位，在进行译码
rdoutmh<='0'&doutmh;--将分的高位数据变为4位，在进行译码
rdouth<="00"&douth;--将时的高位数据变为4位，在进行译码
u1：counter10 port map
     (clk=>clk,reset=>reset,din=>dins(3 downto 0),dout=>doutsl,c=c1);
u2：counter6 port map
     (clk=>c1,reset=>reset,din=>dins(6 downto 4),dout=>doutsh,c=c2);
u3：counter10 port map
     (clk=>c2,reset=>reset,din=>dinm(3 downto 0),dout=>doutml,c=c3);
u4：counter6 port map
     (clk=>c3,reset=>reset,din=>dinm(6 downto 4),dout=>doutmh,c=c4);
u5：counter24 port map
     (clk=>c4,reset=>reset,din=>dinh,dout=>douth);
u6: decoder port map(din=>doutsl,dout=>secondl);--秒低位
u7: decoder port map(din=>rdoutsh,dout=>secondh);--秒高位
u8: decoder port map(din=>doutml,dout=>minutel);--分低位
u9: decoder port map(din=>rdoutmh,dout=>minuteh);--分高位
u10: decoder port map(din=>rdouth(3 downto 0),dout=>hourl);--时低位
u11: decoder port map(din=>rdouth(7 downto 4),dout=>hourh);--时高位
end behav;