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Logic Analyzer 的代码
da5180.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DA5180 IS
PORT(CLK: IN STD_LOGIC;
DAIN1,DAIN2 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DAOUT:OU
sram_adw.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SRAM_ADW IS
PORT(
CLK,EN,SAVE: IN STD_LOGIC;
AIN: IN STD_LOGIC_VEC
mux_trigger.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
addsubc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic U
addsubv.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, overflow flag
-- Project : VHDL Library of Arithmet
subc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic Units
-
subcz.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix subtractor with carry-in, carry-out, zero flag
-- Project : VHDL Library of Arithme
arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
addsubc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, carry-out
-- Project : VHDL Library of Arithmetic U
addsubv.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder-subtractor with carry-in, overflow flag
-- Project : VHDL Library of Arithmet