sram_adw.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 54 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY SRAM_ADW IS
PORT(
      CLK,EN,SAVE: IN STD_LOGIC;
      AIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      DATASOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      ADDOUT: OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
      WRS1: OUT STD_LOGIC
);
END ;

ARCHITECTURE ART OF SRAM_ADW IS
begin
	process(clk, EN)
    VARIABLE WR: STD_LOGIC;
	variable data : std_logic_vector (7 downto 0);
	variable cnt : integer range 0 to 5 ;
	variable cnt2 : integer range 0 to 399 ;
	begin
		if(clk'event and clk = '1') then 
			case cnt is
				when 0 => 
					WR := '0';
				when 1 =>
					IF EN='1' THEN
                        CNT2:=0;
             --       ELSIF CNT2=511 THEN
             --           CNT2:=0;
                    ELSE CNT2:=CNT2+1;
                    END IF;
				when 3 =>
					WR := '1';
                    DATA:=AIN;
                WHEN 5=>
                    IF SAVE='0' THEN
                        CNT:=4;
                    END IF;
				when others =>
					NULL;
			end case;
			cnt := cnt + 1;
		end if; 
    WRS1<=WR;           
  --  ADDOUT<=CONV_STD_LOGIC_VECTOR(CNT2,9);
    DATASOUT<=DATA;
END PROCESS;
ADDOUT<="000000001";
END ART;