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Logic Analyzer 的代码
mux2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART
mux2e.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
mux.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
sram_adw.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SRAM_ADW IS
PORT(
CLK,EN,SAVE: IN STD_LOGIC;
AIN: IN STD_LOGIC_VEC
mux_trigger.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
bus_51.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_51 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
mul2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART
mux2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART
mux2e.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD
mux.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2E IS
PORT(
ADDRESR,ADDRESW: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
ADDRES: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
RDR,WRR,RDW,WRW:IN STD