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library ieee; use ieee.std_logic_1164.all; entity andd is port(x,y:in std_logic; z:out std_logic_vector(1 downto 0)); end andd; architecture andd of andd is begin z

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity warming is port(clk: in std_logic; finishc:in std_logic; warn:out std_logic ); end warming; a

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG30B IS PORT ( Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

--**************************************************************************************************** -- Behavioural model of ABORT generation for ARM core simualtion -- Designed by Ruslan Lepeteno

--**************************************************************************************************** -- Multiplier tester top entity for ARM core -- Designed by Ruslan Lepetenok -- Modified 27.01

--**************************************************************************************************** -- Top entity for ARM Core simulation -- Designed by Ruslan Lepetenok -- Modified 04.02.2003

--**************************************************************************************************** -- Constants for ARM core -- Designed by Ruslan Lepetenok -- Modified 30.01.2003 --**********

--**************************************************************************************************** -- ARM barrel shifter testbench -- Designed by Ruslan Lepetenok --****************************

--**************************************************************************************************** -- Data out register for ARM core -- Designed by Ruslan Lepetenok -- Modified 04.12.2002 --**

--**************************************************************************************************** -- Programm Status Registers for ARM core -- Designed by Ruslan Lepetenok -- Modified 23.01.20