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Logic Analyzer 的代码
testsuite.vhd
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- The Free IP Project
-- VHDL Free-DAC C
cnf_clause.h
/*
HYSDEL
Copyright (C) 1999-2002 Fabio D. Torrisi
This file is part of HYSDEL.
HYSDEL is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public
loadpw.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
mux21w16.vhd
-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Victor
tonetaba.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ;
CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;
HIGH : OU
notetabs.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY NoteTabs IS
PORT ( clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
AR
top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( CLK12MHZ1,HORL1 : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(
mux21a.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux21a IS
PORT( CLK12MHZ2,HORL2 : IN STD_LOGIC;
INDEX3 : IN STD_LOGIC_VECTOR(7 DOWNTO