mux21a.vhd

利用VHDL编写的电子琴发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux21a IS
PORT(       CLK12MHZ2,HORL2 : IN STD_LOGIC;
               INDEX3       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               CODE2        : OUT INTEGER RANGE 0 TO 15;
               HIGH3        : OUT STD_LOGIC; 
               NUME3        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);	             
               HIGH4        : OUT STD_LOGIC; --高8度指示
               IO_DS1       : OUT STD_LOGIC_VECTOR(6 DOWNTO 1);
                 s          : IN STD_LOGIC;
                 y          : OUT STD_LOGIC);
 

END;
ARCHITECTURE ONE OF mux21a IS
   COMPONENT TOP
    PORT (  CLK12MHZ1,HORL1 : IN STD_LOGIC;
               INDEX1       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               CODE1        : OUT INTEGER RANGE 0 TO 15;
               HIGH1        : OUT STD_LOGIC; 
               NUME1        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);			   
               SPKOUT1      : OUT STD_LOGIC;
               IO_DS        : OUT STD_LOGIC_VECTOR(6 DOWNTO 1) );
              
    END COMPONENT;
   COMPONENT Songer
    PORT (   CLK12MHZ   : IN STD_LOGIC;             --音调频率信号         
             --CLK8HZ   : IN STD_LOGIC;               --节拍频率信号
             CODE3    : OUT iNTEGER RANGE 0 TO 15;-- 简谱码输出显示
               HIGH2    : OUT STD_LOGIC; --高8度指示
             SPKOUT2    : OUT STD_LOGIC );--声音输出
   END COMPONENT;
SIGNAL A,B:STD_LOGIC;
--SIGNAL SPKOUT5      : STD_LOGIC;
--SIGNAL SPKOUT3      : STD_LOGIC;
SIGNAL     a0,b0		:iNTEGER RANGE 0 TO 15;
BEGIN
IO_DS1<="001001";
     --y<=SPKOUT3 WHEN s='0' ELSE SPKOUT5;
u1 : TOP 	PORT MAP (INDEX1=>INDEX3,HIGH1=>HIGH3,
NUME1=>NUME3,SPKOUT1=>A,CLK12MHZ1=>CLK12MHZ2,HORL1=>HORL2,CODE1=>a0);
u2 : Songer PORT MAP (HIGH2=>HIGH4,SPKOUT2=>B,CLK12MHZ=>CLK12MHZ2,CODE3=>b0);
y<=A WHEN S='0' ELSE B;
CODE2<=a0 WHEN S='0' ELSE b0;
END ONE;