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Logic Analyzer 的代码
testbcd.vhdtst
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity TestBCD is
end TestBCD;
architecture Stimulus of TestBCD is
file RESULTS: text open
utility.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package UTILITY IS
function fparity (vtctp : std_logic_vector) return std_logic;
end Utility;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ledy.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ledy is
port(clkin:in std_logic;
rst:in std_logic;
q:out std_logic_vector(0 to 7));
end ledy;
architecture behave of ledy is
begin
pro
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
picoblaze_amp_adc_control.vhd
--
-- KCPSM3 reference design - PicoBlaze controlling the two channel programmable
-- amplifier type LTC6912-1 and two channel A/D converter type LTC1407A-1 from
-- Linear Technology.
--
-- Des
program.txt
liberary ieee;
use ieee.std_logic_1164.all;
entity contraler is
port( clock:in std_logic;
light1,light2,light3,pause:out std_logic;
contral:out std_logic;
pause:in std_logic;
run,start
fulladder.tdf
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is port(
a1,a2,c1: in std_logic;
c2,b: out std_logic);
end adder;
architecture behav of fulladder is
begin
b
lms.vhi
-- VHDL Instantiation Created from source file lms.vhd -- 20:16:08 07/03/2005
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_lo
test2.vhd
-- VHDL Test Bench Created from source file lms.vhd -- 20:25:36 07/03/2005
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
core.tpl
[COREGEN.VERILOG Component Instantiation.cosfunc]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change th