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hdpdeps.ref
V1 15
FL E:/sk/iseobject/ex/sk/receive.vhd 2006/04/12.14:28:10
EN work/RECEIVE FL E:/sk/iseobject/ex/sk/receive.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_
shift.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
i2c_master_top.vhd
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level
mult2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult2 is
generic(a1:natural:=9;
b1:natural:=12;
q1:natural:=16);
port(clk:in std_logic;
res
adjust1_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all;
entity adjust1_mult is
port(
clk:in std_logic;
resetn:in
mult3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult3 is
generic(a1:natural;
b1:natural;
q1:natural);
port(clk:in std_logic;
resetn:in std_
adjust3_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all; ------- 包体在所有的程序中要放在最前面----
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mt48lc8m16a2 is
generic(
addr_bits : integer := 12;
data_bits : integer := 16;
col_bits : integer := 9;
adjust2_mult.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all;
entity adjust2_mult is
port(
clk:in std_logic;
resetn:in s
finping8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenping8 is
port(clk_4m:in std_logic;
clk14,clk15:out std_logic);
end;
architecture art of fenp